The 1 capacitor-1 transistor memory cell is used for high packing density DRAM and the memory array using this cell is fabricated by the folded bit line method.
In the layout using the folded bit line method with 1 transistor cell, the transistor and the storage capacitor are placed side by side and between the transistor and the storage capacitor, a minifield oxidation area is grown and the source of said transistor is connected to the arsenic implanted layer on the silicon surface below said storage capacitor, which acts as the electrode of said capacitor.
However, in this method, the oxidation layer for the surface isolation layer of the first polysilicon overlapped on said capacitor area is formed at the same time as the minifield oxidation, and the lateral diffusion of said implanted arsenic under the minifield oxide on the silicon surface is used for the method of connection of the source of said transistor with the arsenic implanted layer which acts as the electrode of said capacitor. However, the doping concentration of said implanted arsenic may be lowered during the minifield oxidation due to the low diffusion coefficient of arsenic.
As a result, the large resistance between the capacitor electrode and the transistor causes the reduction of the margin of a DRAM supply voltage and a rapid decrease of refresh time, and it does not operate at high speed and at worst, said capacitor electrode and the transistor are disconnected in failure.